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ST22N144
Smartcard 32-Bit RISC MCU with 144 Kbytes EEPROM JavacardTM HW Execution & Cryptographic Library
DATA BRIEF
PRODUCT FEATURES
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ADVANCED MEMORY PROTECTION - - - Memory Protection Unit for application firewalling and peripheral access control Domain switching securely controlled by protected Context Stack Native/Java, Code/Data memory attributes with 128-byte granularity Java stack with both 16 and 32-bit accesses User and Supervisor mode stacks Security Context Stack
32-BIT RISC CPU WITH 24-BIT LINEAR MEMORY ADDRESSING 368 KBYTES USER ROM 12 KBYTES USER RAM 144 KBYTES USER EEPROM DUAL INSTRUCTION SET, JAVACARDTM AND NATIVE 4-STAGE PIPELINE 16 GENERAL PURPOSE 32-BIT REGISTERS, AND SPECIAL REGISTERS 4 MASKABLE INTERRUPT LEVELS SUPERVISOR AND USER MODES CPU SECURITY INSTRUCTIONS - - Dedicated instructions for DES and Triple DES implementation Dedicated instructions (Multiply and Accumulate) for efficient implementation of modular arithmetic and elliptic curves based cryptosystems CRC instruction (ISO 3309 16-bit Checksum)
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32-BIT RISC CPU
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FOUR WORKING STACKS - - -
Figure 1. Delivery Form
4 4
SECURITY
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4
Micromodule
4
Wafer
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RANDOM NUMBER GENERATOR EEPROM FLASH PROGRAMMING MODE CLOCK AND POWER MANAGEMENT VOLTAGE AND CLOCK FREQUENCY SENSORS
October 2004
For further information contact your local ST sales office.
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ST22N144
CRYPTOGRAPHIC LIBRARY The Crypto Library is provided as a separate ROM area with an access through a unique entry point. This library provides optimized -for the SmartJ core- and secured implementation of the following features:
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MEMORY
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HIGHLY RELIABLE CMOS EEPROM TECHNOLOGY - - - Error Correction Code for single bit fail within a 32-bit word 10 years data retention, 500,000 Erase/ Write cycles endurance 1 to 128 bytes Erase or Program in 2 ms typical Dual memory buses for data and instruction Byte, Short (2) and Word (4) load and store Address auto-increment
ASYMMETRICAL ALGORITHMS - - - RSA signature/verification Prime number generation (up to 1024-bit) RSA key computation (up to 2048-bit) SHA-1 - -
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HIGH PERFORMANCE MEMORY -
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HASH FUNCTION - SYMMETRICAL ALGORITHMS - DES, Triple DES, AES
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CRYPTOGRAPHY PERFORMANCE The following table provides the cryptographic performances of the ST22N144 based on ST Crypto Library. Table 1. Preliminary Cryptographic Performances
Algorithm RSA 1024 bits RSA 2048 bits DES SHA-1 AES-128 Function Signature with CRT Signature without CRT(2) Verification (e=0x10001) Signature with CRT Signature without CRT Verification (e=0x10001) Triple Single 512-bit Block Encryption including subkey computation Time(1) 79.0 ms 242.0 ms 3.6 ms 485.0 ms 1.7 s 11.0 ms 18 s 8 s 194 s 85 s
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OTHER FEATURES HARDWARE ASYNCHRONOUS SERIAL INTERFACE (ASI) - - 1M baud rate capability 2 serial I/O ports compatible ISO 7816-3 T=0 and T=1
2 USER CONFIGURABLE 12-BIT AND 16BIT TIMERS WITH INTERRUPT CENTRAL INTERRUPT CONTROLLER WITH UP TO 16 INPUT LINES EXTERNAL CLOCK FROM 1 MHz TO 10 MHz 1.62 V TO 5.5 V SUPPLY VOLTAGE TEMPERATURE RANGE -25 C to +85 C POWER SAVING STANDBY MODE ESD PROTECTION GREATER THAN 5000 V UNIQUE IDENTIFICATION PER DIE TYPICAL INTERNAL FREQUENCY UP TO 33 MHz SOFTWARE CONTROLLED CLOCK MANAGEMENT
1. Internal clock at 33 MHz 2. CRT: Chinese Reminder Theorem
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DESCRIPTION The ST22N144 is a member of the SmartJTM platform using a 32-bit Reduced Instruction Set Computer (RISC) core to execute both Native RISC instructions and JavaCardTM 2.x Technology instruction (byte codes) directly (See Figure 2. "SmartJTM Platform EEPROM Architecture", on page 3). Direct JavaCardTM byte code execution provides high performance advantage over processors that emulate the JavaCardTM byte code instruction set. The product features a 24-bit wide linear addressing capability and includes User ROM, User RAM, and User EEPROM. Memory and Peripheral accesses are controlled by a Memory Protection Unit that allows to implement firewalls between applications. Memories are accessed via two different buses, allowing simultaneous accesses to code and data. Memory load and stores can be performed at byte, short (2-bytes), or word (4-bytes) granularity, with optional pointer auto increment. The ST22 core includes dedicated instructions to accelerate performances of the following algoriths: - - - - DES and Triple DES Modular Arithmetic on big numbers, Characteristic two field arithmetic to support efficiently Elliptic Curves, CRC 16-bit ISO 3309.
The product has clock and power management, 2 User configurable Timers, a Central Interrupt Controller and a Random Number Generator.
Figure 2. SmartJTM Platform EEPROM Architecture
SECURITY
TIMER
POWER MANAGEMENT RAM
RNG
PERIPHERALS 32-bit RISC CORE MPU BUS 2 BUS 1
ROM CLOCK MANAGEMENT
EEPROM
ASI
ISO 7816
...
...
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The product has two execution modes. Java mode is used when JavaCardTM 2.x byte codes are being executed. Native mode is used for long JavaCardTM byte codes, Native methods and system routines. The processor enters Java mode when a dispatch (DISP) instruction is encountered. When executing in Native mode, there are two privilege levels, User and Supervisor. Some instructions can only be executed in Supervisor mode. Instructions are of variable length, from 1 to 4 bytes in Native mode. Special instructions exist for single-cycle stack operations, a frequent occurrence in Java code. Short branches and conditional branches within a 1 KByte block or the entire 16-MByte instruction space are supported. The product has four stages of pipeline in Native mode: fetch, decode, execute and write-back. In Java mode, there are five stages of pipeline: byte code-fetch, byte code-decode, decode, execute and write-back. The CPU core has 16 32-bit general purpose registers, as well as special registers of variable length. The chip also features a very high performance Asynchronous Serial Interface (ASI) to support high speed serial communication protocols compatible with ISO 7816 standard. It is manufactured using the highly reliable ST CMOS EEPROM technology. EMBEDDED SOFTWARE The Hardware Software Interface (HSI) implements the Hardware abstraction layer. It consists of C interfaces to the EEPROM memory and peripherals. The drivers are: - - - - - - - - - Non Volatile Memory Asynchronous Serial Interface Central Interrupt Controller Timer Random Number Generator Clock Manager Memory Protection Unit Sensors Security
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Note: - The HSI driver software layer is a C-oriented API allowing efficient and secure access to the peripherals and Non Volatile Memory for programming or erasing. Only the OS and JavaCardTM Virtual Machine (JVM) domains can access the HSI software layer (In the following the term OS will refer to the software layer that is directly interfaced to the HSI).
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CRYPTOGRAPHIC LIBRARY ST proposes a complete set of firmware subroutines to allow fast and easy implementation of cryptographic protocols. These subroutines have been optimized according to the ST22 core specificities and dedicated instructions. Security issues have been addressed to provide state of the art security. The whole library is located in a specific ROM area access through a single entry point. Following features are available through library:
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ASYMMETRICAL ALGORITHMS: - Basic modular arithmetic for various lengths including modular product for odd modulus. More elaborate functions (with separate fast and secure versions) such as exponentiation, RSA signatures and verifications for modulo length up to 2048 bits long. Full internal RSA key generation. This guarantees that the secret key will never be known outside the chip and will contribute to the overall system security, Random number generation of big size, SHA-1. DES, Triple DES including key schedule, AES with standalone key schedule for lenght 128, 192 and 256.
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SYMMETRICAL ALGORITHMS
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SOFTWARE DEVELOPMENT ENVIRONMENT Modularity, flexibility and methodology are the key words for the SmartJTM Development Tools Platform. Using the same interface, the developers are able to create, compile and debug a project. The SmartJTM Integrated Development environment (IDE) includes: - A code Generation chain: C/C++ compiler, assembler and linker. The assembler supports both native and JavaCardTM instruction sets.
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An instruction set simulator, a cycle accurate simulator, a C/C++ source level debugger. Software and Hardware tools allow to efficiently generate, then validate all code and application embbeded softwares for the SmartJTM platform.
Figure 3. SmartJTM IDE
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Figure 4. SmartJTM Code Generation Tools
C /C + + S o u rc e
A s m S o u rc e
C / C + + C o m p ile r
N a t iv e /J a v a A s s e m b le r
C /C + + S ta n d a rd L ib r a rie s
O b je c t F ile s
HSI L ib r a r y
C ry p to . L ib r a ry
L in k e r
D e v ic e S e t - u p
A p p lic a tio n
S C P 1 6 0 c/P R Z
Figure 5. SmartJTM Code Validation Tools
Integrated Development Environment
> Console.exe
Debugger GUI
Third party tools
ST PLAYER
PC/SC Virtual interface
DEBUGGER CORE
Cycle accurate Simulator
Instruction Set Simulator
Monitor
...
Random
Timer
ASI
FPGA Board
SmartCard Reader
SmartCard Pod
160d
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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